IBM unveiled a sub-1 nanometer chip architecture called nanostack, packing nearly 100 billion transistors at the 0.7 nm node, presented at VLSI 2026. The three-dimensional design delivers up to 70% greater energy efficiency and nearly twice the transistor density of IBM's 2021 2 nm chip, targeting artificial intelligence accelerator workloads with a 40% improvement in SRAM scaling. IBM Research projects the nanostack architecture supports at least a decade of continued semiconductor scaling, addressing mounting industry pressure as traditional two-dimensional shrinking hits physical constraints including quantum tunneling and heat dissipation.
IBM Introduces Three-Dimensional Nanostack Transistor Architecture
The announcement centers on the nanostack, a three-dimensional transistor architecture developed at IBM's semiconductor research facility in Albany, New York. The design stacks and staggers transistors vertically in two bonded layers, using an ultra-thin dielectric material to separate them. That approach differs fundamentally from the nanosheet technology IBM pioneered and the broader industry adopted—nanosheets compressed features in two dimensions, while nanostack adds density in a third.
"We're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency," said Jay Gambetta, Director of IBM Research and IBM Fellow.
Nanostack Chip Delivers Nearly 2x Density and 70% Energy Efficiency Gain
IBM's published technical results, presented at VLSI 2026, report the following compared to IBM's 2 nm chip from 2021:
- Nearly 2x transistor density
- Up to 50% more performance
- Up to 70% greater energy efficiency
- 40% improvement in SRAM scaling
The SRAM gain matters specifically for AI workloads. On-chip memory bandwidth is a limiting factor for AI accelerators, and better SRAM scaling lets chip designers fit more memory closer to the processor without adding area or power draw.
IBM Clarifies 0.7 nm Node Designation Reflects Density Generation
Modern process node numbers no longer correspond to literal physical dimensions. The transistor channel layers in IBM's nanostack design measure roughly 5 nanometers thick, or about 15 silicon atoms. The 0.7 nm designation reflects the density and performance generation, not a direct measurement of every feature on the chip. IBM acknowledged this directly, stating that the nanostack method delivers the effective gains expected from sub-1 nm scaling by going vertical rather than by shrinking every dimension closer to atomic limits.
IBM Projects Nanostack Supports Decade of Continued Scaling
The semiconductor industry has faced mounting pressure as traditional two-dimensional shrinking hits physical constraints, including quantum tunneling, heat dissipation, and manufacturing cost. The pace of gains from pure lithography improvements has slowed. IBM's approach addresses this by adding density through 3D sequential integration. The company projects the nanostack architecture can support at least a decade of continued scaling from this point.
Dan Hutcheson of Techinsights said the development puts "another 10, 15 years on the roadmap." Major competitors like Intel, Samsung, and TSMC are pursuing related three-dimensional transistor strategies, including complementary FET designs. IBM's announcement represents a working demonstration of a verified path at the sub-1 nm threshold.
IBM Conducts Research at Albany Facility With Industry Partners
IBM conducts this work alongside partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. The Albany facility will also house a High Numerical Aperture Extreme Ultraviolet lithography tool from ASML, a system required for the next phase of logic scaling. IBM separately announced plans to form Anderon, a standalone quantum foundry intended to manufacture quantum wafers at commercial scale.
IBM Sees Path to Production in Five Years
The nanostack chip remains a research prototype, though IBM confirmed it has demonstrated functional CMOS inverter operation with expected switching performance. IBM sees a path to production adoption in as early as five years. The announcement does not signal an imminent product release—it signals that the industry's next generation of hardware has a viable structural foundation.
FAQ
What did IBM unveil at VLSI 2026?
IBM unveiled a sub-1 nanometer chip architecture called nanostack at VLSI 2026, packing nearly 100 billion transistors at the 0.7 nm node with a three-dimensional design that stacks transistors vertically in two bonded layers.
How does IBM's nanostack chip compare to its 2021 2 nm chip?
IBM's nanostack chip delivers nearly 2x transistor density, up to 50% more performance, up to 70% greater energy efficiency, and a 40% improvement in SRAM scaling compared to IBM's 2 nm chip from 2021.
When does IBM project the nanostack chip will reach production?
IBM sees a path to production adoption in as early as five years, with the nanostack architecture projected to support at least a decade of continued semiconductor scaling.
