IBM Unveils 0.7nm Nanostack Chip With 100 Billion Transistors, Achieves 70% Energy Efficiency Gain

IBM announced on June 25 its nanostack chip at the 0.7 nanometer node, featuring nearly 100 billion transistors with a three-dimensional vertical architecture. Compared to IBM's 2 nm chip from 2021, the new design delivers nearly 2x transistor density, up to 50% greater performance, and up to 70% energy efficiency improvement, with 40% better SRAM scaling. The 3D stacked-transistor approach, developed at IBM's Albany, New York research facility and presented at VLSI 2026, addresses on-chip memory bandwidth limitations for AI accelerators.

IBM sees a path to production adoption within five years, around 2031. The company projects the nanostack architecture can support at least a decade of continued semiconductor scaling, extending Moore's Law as traditional two-dimensional shrinking faces physical constraints. The chip remains a research prototype with demonstrated functional CMOS operation.