Google's Next-Generation TPU 'Humufish' Switches from TSMC CoWoS to Intel EMIB-T Packaging

According to a latest report from SemiAnalysis, Google's next-generation tensor processing unit (TPU), codenamed "Humufish," will abandon TSMC's legacy CoWoS advanced packaging technology and adopt Intel's latest EMIB-T 2.5D packaging process. The move marks Intel's first success securing a hyperscale cloud customer for its advanced packaging solutions.

Intel's EMIB-T employs silicon bridges between chips to replace costly large-area silicon interposers, offering lower costs and better scalability. The new variant incorporates through-silicon vias (TSV) technology for heterogeneous integration and HBM stacking. Intel expects EMIB-T to achieve 8 to 10 times reticle size complexity by 2026, with competitive manufacturing density and yield rates. Google's transition addresses TSMC's persistent CoWoS capacity constraints—the conventional process limits interposer size to approximately 3.3 times reticle dimensions and continues facing supply shortages.