AMD unveiled its new AI accelerator, the Instinct MI455X, at its annual event “AMD Advancing AI 2026,” held on July 22 at the Moscone Convention Center in San Francisco, California. Compared with the previous-generation MI355X (with 8-layer stacked HBM3E and 288GB capacity), capacity is up 1.5x and speed is up 2.9x.
HBM4 specs for AMD MI455X
The HBM4 specs built into the MI455X are driven by the following key improvements:
· Generation comparison (MI455X HBM4 vs MI355X HBM3E)
· Number of stacked layers: 12 layers vs 8 layers (+4 layers)
· Per-die capacity: 432GB vs 288GB (up 1.5x)
· Bandwidth: 23.3 TB/s vs about 8 TB/s (up 2.9x)
· Channel width: 2048 bits vs 1024 bits (doubled)
· Overall compute performance: about 4x higher than the previous generation
Dieckmann explained that the speedup isn’t achieved purely by increasing clock frequency, but instead by increasing the number of stacked layers (8 layers → 12 layers) and simultaneously doubling the connected channel width (1024 bits → 2048 bits).
System integration for MI455X: 256GB/s direct CPU-to-access
The CPU paired with the MI455X is AMD’s 6th Gen server processor (EPYC Gen6). It connects directly to the GPU via a dedicated channel, with data transfer speeds up to 256GB/s—enabling the CPU to access GPU memory without latency and eliminating data-exchange bottlenecks. At the Helios system level, a single rack can integrate up to 72 MI455X units, with total HBM4 capacity reaching 31TB. Memory bandwidth can reach 1.7 PB/s, bringing chip-level memory performance gains up to rack-level scalability.
Samsung Electronics as the main HBM4 supplier
A senior AMD executive interviewed on-site said that Samsung Electronics will supply most of the HBM4 memory for the MI455X. Samsung’s prepared HBM4 product uses a 12-layer stacking design, with capacity in the 36GB class, using a 10nm process (1c). Per-lane transfer rate is 13Gbps, and per-stack bandwidth is 3.3TB/s—reportedly much faster than the previous generation HBM3E.
AMD and Samsung Electronics signed an MOU in March 2026 at Samsung’s Pyeongtaek office location to expand cooperation in the HBM4 field. The AMD executive also said the partnership will be further strengthened in the next-generation HBM4E phase, targeting 16 stacked layers, about 60GB capacity, and bandwidth in the tens of TB/s.
FAQ
What are the HBM4 memory specs on AMD MI455X, and how do they compare with the previous-generation MI355X?
MI455X features 12-layer stacked HBM4 with 432GB per die and 23.3 TB/s bandwidth. Compared with the previous-generation MI355X featuring 8-layer stacked HBM3E (288GB capacity), capacity increases 1.5x and speed increases 2.9x; overall compute performance is about 4x higher than the previous generation.
What role does Samsung Electronics play in supplying HBM4 for AMD MI455X?
Based on statements from an AMD executive during an on-site interview, Samsung Electronics will provide most of the HBM4 memory for the MI455X. Samsung’s HBM4 product uses 12-layer stacking with 36GB capacity, uses a 10nm process (1c), and reaches 3.3TB/s per-stack bandwidth. AMD and Samsung Electronics also signed an MOU in March 2026 to expand cooperation, and will jointly develop the next-generation HBM4E.
When did the MOU between AMD and Samsung Electronics get signed, and what is the scope of collaboration?
AMD and Samsung Electronics signed a memorandum of understanding (MOU) in March 2026 at Samsung’s Pyeongtaek office location, aiming to expand cooperation in the next generation of memory (including HBM4). The two will also jointly develop HBM4E (7th-generation HBM), targeting 16 stacked layers, about 60GB capacity, and bandwidth in the tens of TB/s.
