Who is competing for CoWoS?

If the main theme of the semiconductor industry over the past decade and a half was “Moore’s Law,” then the loudest keyword today must be advanced packaging.

As large-model parameters have surged from the tens of billions to the trillion-level, the path of relying solely on process-node shrink to improve compute power is nearing physical limits. An AI chip has to accommodate both a massive number of compute units and high-bandwidth memory at the same time—traditional 2D packaging can no longer keep up. As a result, the golden combo of HBM + CoWoS has effectively become a must-have option for nearly all makers of high-end AI chips.

From NVIDIA’s Blackwell-architecture GPUs to AMD’s MI series accelerators, and to the training chips developed in-house by cloud providers—whoever can secure enough CoWoS capacity will truly be able to stand firm in the AI compute race.

A “positioning battle” centered on TSMC’s CoWoS packaging capacity has quietly begun among global chip giants.

Why is CoWoS non-negotiable?

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s 2.5D advanced packaging technology developed in-house. In simple terms, it no longer welds chips and memory directly onto the substrate. Instead, it places GPU/ASIC-type compute chips side by side with HBM memory chips on a single interposer layer, using high-density TSVs (through-silicon vias) and micro-bump interconnects. High-speed interconnection between chips is achieved through dense, fine wiring inside the interposer, and the whole assembly is then packaged onto the substrate.

Image source: Dao to Jian is not simple

Why go through all this trouble? Traditional PCB circuit boards have wiring line widths that are too thick, limiting signal transmission distance and speed. A single GPU often needs to connect to multiple HBM chips, with bandwidth demands reaching several terabytes per second. Only the ultra-fine wiring of a silicon interposer can handle such enormous data throughput.

In 2011, TSMC formally introduced CoWoS. After multiple rounds of iteration, three categories have taken shape: CoWoS-S (a full-piece silicon interposer), CoWoS-R (RDL interposer layer), and CoWoS-L (a local silicon bridge + organic substrate). Among them, CoWoS-L is the mainstream solution today—using “local silicon bridges” to replace an ultra-large monolithic silicon interposer, reducing warpage and cost while supporting larger package area and more HBM stacking.

The core advantages of this architecture are very clear:

• Bandwidth boost: HBM and the GPU are directly interconnected via the silicon interposer. Bandwidth can reach dozens of times that of traditional DDR, completely solving the “memory wall” problem in AI training;

• Lower power consumption: The signal transmission distance is dramatically shortened, significantly reducing data-movement power;

• Higher integration: Multiple Chiplet compute chips + multiple HBM modules can work together in the same package, breaking through the area limitation of a single chip.

It could be said that without CoWoS, perhaps there would be no today’s AI training chips with parameters in the order of hundreds of billions to trillions.

Who is抢 CoWoS?

According to Morgan Stanley’s supply-chain research and forecasts, the total global CoWoS wafer demand from key customers will be about 1.38M wafers in 2026, rising to 2.68M wafers in 2027—nearly doubling over two years. The participants in this capacity contest have long expanded beyond single GPU manufacturers to the entire AI compute supply chain.

Global CoWoS capacity demand forecast by key customers

NVIDIA: Still the main character, but its share is thinning

It’s not hard to see that NVIDIA remains the absolute lead.

In 2026, NVIDIA’s CoWoS capacity demand is 780k wafers, jumping to 1,200k wafers in 2027 and remaining #1. From Hopper to Blackwell and the latest Rubin architecture, each GPU generation is deeply tied to TSMC’s CoWoS-L process.

Meanwhile, CoWoS-R is mainly used for NVIDIA’s Vera CPU production, with expected shipments of 5.75 million units. The strong reservation indicates Vera CPU shipments will nearly double, driving CoWoS-R demand of more than 10k wafers. CoWoS-S is used for Quantum and Spectrum switch chips.

Overall, NVIDIA alone captures more than half of TSMC’s CoWoS capacity.

But it’s worth noting that NVIDIA’s share of overall demand will decline from around 56% in 2026 to around 45% in 2027—while absolute demand increases, the share is being diluted. This means the CoWoS market structure is shifting from “NVIDIA dominates alone” to multiple strong players coexisting.

AMD: The biggest dark horse in 2027, pursuing NVIDIA’s incremental demand directly

If NVIDIA is the king of existing volume, then AMD is the most aggressive pursuer.

AMD’s CoWoS capacity in 2026 is only 130k wafers, surging to 2.68M wafers in 2027. The 2.68M-wafers incremental increase is almost the same as NVIDIA’s (442k). The main drivers are AMD’s MI series AI server chips ramping, and the large-scale adoption of 3D V-Cache and the Chiplet architecture—making AMD’s CoWoS demand more than triple within a year (growth of 307%).

It’s reported that AMD’s key products in 2027 will include MI455, with limited production of MI500 (Arcadia) toward year-end. For AMD’s Venice CPU segment, AMD mainly relies on CoWoS processes from non-TSMC suppliers such as ASE/SPIL and Amkor, with capacity rising from 50k wafers to 270k wafers. This is expected to correspond to 6.75 million CPU units, mainly driven by Agentic AI demand.

Interestingly, the 10k-wafers CoWoS demand from Xilinx that was acquired by AMD remains unchanged. This likely suggests the growth comes entirely from AMD’s own product lines exploding, while FPGA product lines’ CoWoS demand seems to be saturated, or the technical route may be shifting to other packaging approaches.

Broadcom: Steady growth for network chips

In 2026, Broadcom’s capacity demand is 300k wafers, making it the second-largest CoWoS demander; in 2027, it is expected to grow to 2.48M wafers (year-on-year growth of 61%), overtaken by AMD to become #3.

Unlike the top two, Broadcom’s main products are not GPUs, but high-end network switch chips. AI clusters’ demand for 800G and 1.6T switches is surging, pushing Broadcom’s Tomahawk series chips to fully shift toward CoWoS advanced packaging. In addition, Broadcom is also helping design and manufacturing Google TPU v7 (Ironwood) and v8i (SunFish) chips, occupying CoWoS capacity.

MediaTek makes an unexpected breakout

MediaTek jumps from 250k wafers to 180k wafers, a growth of 350%. MediaTek’s surge is the most surprising highlight on this list. This traditional mobile chip giant is making a major push into the AI accelerator market. Cloud and edge ASIC chips are starting to adopt CoWoS at large scale, and its growth speed ranks #1 among all top customers.

Some suppliers disclose that MediaTek’s ASIC business mainly comes from Google TPU v8t (ZebraFish), expected to correspond to shipments of 3.6 million units.

AWS: In-house chips from cloud providers steadily scaling up

AWS’s two in-house chip product lines (Annapurna and Alchip) combined demand rises from 88k wafers to 126k wafers, reflecting the continued iteration of Trainium training chips and Inferentia inference chips. This represents cloud providers’ determination to move away from reliance on a single GPU vendor—though the growth rate is relatively gentler than top-tier vendors.

Marvell and GUC: Customized ASICs brewing quietly

Marvell grows from 17k wafers to 64k wafers, and GUC increases from 160k wafers to 60k wafers—growth of 276% and 329%, respectively. These two spikes reflect a trend: the customized AI ASIC market is exploding. Marvell’s DPU and AI networking chips, and CREATIVE ELECTRONICS (GUC)’s ASIC design services business, are both consuming large amounts of CoWoS capacity.

More and more internet companies are choosing to develop AI chips in-house, and they all need to connect to TSMC’s packaging capacity through design-service providers.

Cisco: Growth stalls in the traditional track

Cisco has a smaller scale and growth increase: demand only rises from 200k wafers to 200k wafers, reflecting limited pull from traditional networking equipment and mid-to-low-end FPGAs on high-end CoWoS. This portion of the market is gradually being squeezed by AI-related demand.

Overall, the demand structure for CoWoS is undergoing profound change:

• AI GPU camp is the base: NVIDIA + AMD + Broadcom account for the vast majority of capacity;

• ASIC and networking chips are the new increments: MediaTek, Marvell, and GUC benefit from demand for AI switch chips and high-speed interconnect chips. Packaging demand doubles, with growth far exceeding the industry average;

• In-house chips from cloud providers are a long-term variable: Although the current scale isn’t very large, cloud in-house large-model chips are continuously expanding capacity. This also represents a direction toward decentralizing the compute supply chain;

• Traditional FPGA/network equipment: Xilinx and Cisco see demand stall, and traditional business provides limited pull on high-end CoWoS.

From the perspective of total industry volume, global top key customers’ CoWoS capacity demand increases from about 442k wafers in 2026 (combined) to about 50k wafers in 2027 (combined), for overall growth of about 94%. Over the two years, global CoWoS wafer demand nearly doubles, validating Morgan Stanley’s judgment of high growth in the advanced packaging segment.

When every player crowds onto the same track, the issue of capacity shortage naturally comes to the surface.

Capacity bottleneck: TSMC runs fast enough—but not fast enough

TSMC, which had long realized the strategic value of CoWoS, has been expanding capacity relentlessly.

According to data statistics, TSMC’s CoWoS monthly capacity was only about 10k wafers in 2022, but by 2025 it had pushed close to 70k wafers. With TSMC and its partners actively expanding, TSMC’s CoWoS monthly capacity in 2026 is expected to reach a record 120k to 140k wafers. In 2027, it will further rise to 170k wafers per month (some plans show that by end of 2027 capacity could reach 200k wafers per month). The expansion is mainly focused on Tainan and Chiayi, with the scale of expansion far exceeding prior levels.

While expanding CoWoS, TSMC is also actively advancing CoPoS (Chip on Panel on Substrate), a panel-level packaging technology industry-leading in its own right. The pilot production line is expected to complete commissioning by June 2026, and earliest mass production could be achieved in 2028 to 2029, in order to respond to packaging needs for large-die chips.

Beyond TSMC, other camps are also expanding capacity. By end of 2027, CoWoS capacity outside the TSMC camp (ASE/SPIL, Amkor, etc.) is expected to expand to 80k wafers per month (80kwpm). Among them, ASE/SPIL increases from 30kwpm at the end of 2026 to 50kwpm, and Amkor rises from 20kwpm to 30kwpm—both focusing on CoWoS-L and CoWoS-R.

It can be seen that the industry supply structure is starting to shift from TSMC’s single-point dominance to parallel capacity expansion by foundry and OSAT players. UBS expects CoWoS industry monthly capacity will grow from 160k wafers at end of 2026 to 250k wafers at end of 2027, a year-on-year increase of about 56%. Behind this round of expansion, Rubin, AMD Venice, Google TPU, and Amazon Trainium are simultaneously increasing packaging demand.

At the same time, over the next five years, TSMC’s CoWoS will continue developing on a yearly schedule of further scaling to integrate more logic and HBM. In 2026, it produced the world’s largest CoWoS with a 5.5x reticle size; yields exceed 98%. The 14x reticle-size CoWoS designed to integrate 20 HBM modules will enter mass production in 2028, and a version that can integrate 24 HBM modules with a reticle size larger than 14x is expected to be ready in 2029.

Supply chain disclosures indicate that not only is CoWoS demand strong, but TSMC’s progress on SoIC and CoPoS is also moving quickly, making visibility into equipment-supply-chain orders reach as far as 2030. For example, TSMC’s SoIC capacity is also continuously expanding. Previously, it was estimated that 2027 monthly capacity would be lifted from 10k wafers to 20k wafers; the latest reports say it has been raised to 50k wafers, with NVIDIA securing a large portion of the capacity.

However, new capacity will soon face a bigger order pool.

According to UBS calculations, total CoWoS capacity demand will rise from 270k wafers in 2026 to 10k wafers in 2027 (the Morgan Stanley forecast above is 1.6T wafers). That is about 89% growth in one year—clearly faster than the increase in monthly industry capacity in the same period.

Image source: UBS

Supply chain disclosures say that currently the CoWoS supply-demand gap is about 20%, and it is expected to narrow to about 10% only by end of 2026. Another institution’s calculations suggest that the capacity gap in 2027 could expand to 700k wafers, exceeding 30%.

Some supply-chain companies point out that even if CoWoS monthly capacity is raised to 200k+ wafers, it is still difficult to satisfy all customer order demand. In addition, there are still risks such as expansion delays, monopolization, and onshoring manufacturing in the U.S. Many customers have moved from previously relying almost exclusively on TSMC to listing Amkor, ASE, and others as spillover order recipients, building a second advanced packaging supply path.

On the other hand, there are other reasons why expansion speed can’t keep up with demand. First, the process threshold is high. CoWoS involves multiple advanced and precise processes, such as large-size silicon interposers, TSV through-silicon vias, and micro-bump bonding. Yield ramp-up takes time. Second, the equipment supply chain is long. Bonding tools and inspection equipment required for advanced packaging have lead times of over one year; it isn’t possible to expand instantly just because there is money. At the same time, CoWoS and HBM are mostly tightly coupled. SK Hynix and Samsung’s HBM capacity can’t keep up—no matter how large CoWoS capacity gets, there is still not enough HBM to ship.

This leads to an awkward situation: TSMC’s CoWoS capacity remains full during 2024 to 2026, and order visibility has even been booked out to 2027.

Under these circumstances, to secure capacity, chip makers have no choice but to negotiate with TSMC more than a year in advance, and even industry “unspoken rules” emerge around prioritizing “capacity grabbing.”

Another point that needs attention is that while CoWoS packaging demand is rising, the front-end advanced process is also getting tighter.

UBS notes that the share of cloud AI products in TSMC’s N3 demand will rise from 35% in 2026 to 72% in 2027. Over two years, average capacity utilization rates are about 108% and 109%, respectively. Rubin, Vera CPU, Google TPU, and Trainium all need to first obtain N3 wafers, and only then can they enter the CoWoS packaging stage.

In this process, the customer mix is also changing rapidly. NVIDIA’s expected share of TSMC N3 capacity will rise from 10% in 2026 to 30% in 2027, and Broadcom’s share will rise from 10% to 16%. In the same period, Apple’s share drops from 38% to 14%. Although consumer electronics still exists as demand, cloud AI is clearly increasing dual occupancy of both advanced process nodes and back-end packaging.

Therefore, whether CoWoS supply can keep up depends on whether all these links can ramp up on the same schedule.

The industry’s monthly capacity target of 250k wafers by end of 2027 requires simultaneous delivery and ramp-up of advanced-process wafer supply, OSAT end-to-end yield, bonding and measurement equipment; it also needs Rubin, Venice, and TPU to ramp according to plan. As demand comes from more customers, CoWoS will break free from reliance on a single GPU cycle, but it will also increase product mix and schedule complexity.

Recently, there have been voices in the industry that TSMC has not yet confirmed equipment-makers’ order allocation details. Suppliers are anxious, worried that this could create an atmosphere of price cuts to win orders. Also, from equipment ordering to production and shipment, the timeline is at least 7 to 9 months. The industry worries that it may be difficult to deliver equipment on time.

In addition, more troublesome than capacity is the technology and cost bottleneck.

It is reported that the silicon interposer layer that CoWoS relies on faces three major issues: high cost, limited size, and susceptibility to warpage. For a 12-inch silicon interposer, the per-die cost exceeds $100, accounting for more than half of the total packaging cost. Especially as AI chips get larger—NVIDIA B200’s packaging area is already 3 to 4 times the maximum interposer silicon capacity—this interposer size bottleneck is hard to avoid. The next-generation Rubin GPU will be even larger; currently the only emergency solution is the “local silicon bridge + organic substrate” approach.

Intel and Samsung are sharpening their knives

Tight CoWoS capacity also gives competitors a chance.

CoWoS is not the only answer for 2.5D packaging. Competitors are accelerating their own alternative solutions. Especially Intel and Samsung, which have been fighting for years in advanced process territory, are sharpening their knives in the advanced packaging market—where the market cake is huge and the capacity gap is real.

Intel’s EMIB and Foveros

Intel has its own matrix of 2.5D/3D packaging technologies.

Among them, EMIB (Embedded Multi-die Interconnect Bridge) is actively grabbing market share. Unlike CoWoS, EMIB replaces a full-size interposer layer with a local embedded silicon bridge, enabling local high-speed interconnects between chiplets, with higher yields and dramatically lower costs.

Image source: Qi Ren Revisited

Compared with CoWoS, EMIB uses only one-third to one-fifth of the silicon material, and the cost per unit is 30% to 50% lower. EMIB-M has supported 6x reticle-size designs, with expected reach to 8x to 12x in 2026 to 2027. The risk of thermal expansion mismatch is lower, warpage issues are fewer, and yields have already surpassed 90%.

The EMIB process is also evolving and iterating:

• EMIB (first generation): baseline silicon bridge, targeting general heterogeneous integration of CPU + GPU/HBM.

• EMIB-M (Matrix): multi-bridge arrays. Current is 6x reticle size; the 2026 to 2027 target is 8x to 12x, aiming at ultra-large-scale multi-chiplet AI chips.

• EMIB-T (Through-Silicon Via): silicon bridges introduce TSV for vertical power delivery. Power and signals travel directly from the bottom of the package to the chips, suppressing DC/AC noise crosstalk, matching the strict bandwidth and power requirements of AI accelerators and data-center chips. Post-stage yields have climbed to 90% or above.

• EMIB + glass substrate: launched in early 2026. A giant 78×77mm package (2x standard reticle), with “10-2-10” stacking (800μm-thick glass die + 10 layers of RDL on top and 10 layers at the bottom = 20 circuit layers). Positioned for HPC and AI servers.

Image source: Qi Ren Revisited

On market progress, Intel’s 2026 EMIB-T packaging has already won orders for Google’s next-generation TPU. NVIDIA’s next-gen GPU Feynman also plans to introduce EMIB. Meta also plans to adopt it in 2028 CPUs. SK Hynix is working with Intel to test EMIB to reduce reliance on CoWoS.

Recently, Intel announced the appointment of Lee Seok-hee as Executive Vice President of Intel Foundry, responsible for advanced packaging, system integration, back-end technology development, and back-end manufacturing, reporting directly to CEO Pat Gelsinger.

The key significance of this appointment is that Intel is elevating advanced packaging into an important growth point of its Foundry business. AI accelerators typically need to integrate logic chips, HBM, I/O chips, and other Chiplets into a single package. Packaging platform capabilities directly influence whether customers are willing to adopt Intel Foundry. Intel will independently strengthen back-end packaging capabilities, helping it provide a more complete system-level manufacturing solution beyond its 18A, 14A, and subsequent process nodes.

In terms of global competitive landscape, Intel is not only trying to catch up with TSMC at the front-end process level, but also trying to attract AI ASIC, HPC, and cloud service customers by leveraging back-end technologies such as EMIB, Foveros, EMIB-T, and hybrid bonding. Advanced packaging could become Intel’s entry point to re-enter the high-end customer supply chain.

Some industry participants say EMIB is moving from a CoWoS replacement option to becoming the second pole of packaging for the big-chip AI era. Its “silicon bridge + glass substrate” dual-line evolution is constraining CoWoS’s premium space.

Foveros is Intel’s true 3D stacking technology, enabling stacking logic chip on top of logic chip. With Intel’s IDM 2.0 strategy advancing, its packaging business has also started taking orders externally, directly competing with TSMC’s CoWoS and SoIC.

Samsung’s I-Cube

Samsung’s competitive advantage is that it can provide a complete “turnkey” solution covering HBM manufacturing, logic process foundry, and advanced packaging.

Samsung’s SAINT (Samsung Advanced Interconnect Technology) family covers I-Cube (2.5D) and X-Cube (3D) technologies. Backed by Samsung’s own HBM memory capacity advantage, Samsung is working hard to secure advanced packaging orders from AI chip customers, aiming to form an integrated “memory + packaging” competitiveness.

Image source: Cold-blooded rock

I-Cube uses a silicon interposer to integrate logic chips and HBM. It can already support integration of up to 8 HBM stacks. For next-generation HBM4, Samsung is actively pushing hybrid bonding technology to replace conventional micro-bump stacking, aiming to improve thermal dissipation capability and reduce packaging height. Samsung plans to dramatically increase its HBM monthly capacity to 250k wafers by 2026 in hopes of regaining dominance in the high-performance AI accelerator market.

However, some industry participants say: “Customers adopting Samsung’s 2.5D packaging platform either ship very small volumes or are merely short-term projects lasting only a few months. In the era where advanced packaging determines chip performance, Samsung urgently needs to strengthen competitiveness in this area.”

In response, Samsung is shifting its 2.5D packaging technology route from traditional wafer-level packaging (WLP) to panel-level packaging (PLP). PLP uses square large-area panels, with high area utilization and production efficiency better than circular wafers. As AI chip sizes keep growing, PLP suitability will further improve. Samsung is pushing to change the Cube technology from WLP to PLP and is also working on developing “system-level panels (SoP)” for ultra-large chips. The current development size is 415mm × 510mm.

Diverse routes across industry players

In addition, OSAT giants such as ASE (Amkor? actually ASE is ASE, 日月光) and Amkor are also developing similar 2.5D packaging solutions. While there is still a gap versus CoWoS in the most cutting-edge performance, they have advantages in cost and capacity flexibility, and are eating into the high-end market.

For example, ASE’s VIPack™ platform is designed to support full-scope heterogeneous integration needs ranging from fan-out chip packaging (FOCoS) to CPO (co-packaged optics). To address capacity shortages brought by the AI boom, ASE plans to invest more than $6 billion in capital expenditures in 2025, focusing on expanding CoWoS-related capacity at Kaohsiung and Central Science Park (CSP). ASE also demonstrated advanced silicon photonics technology by integrating optical engines directly into the packaging substrate, significantly improving data transmission efficiency inside AI data centers.

Amkor, as the world’s second-largest OSAT, is focusing its strategy on tightly binding with advanced process foundries. Amkor has signed a memorandum of understanding with TSMC, and will provide packaging and testing support for TSMC at its new plant in Arizona, reducing turnaround time for wafer shipping across the Pacific. Amkor’s R&D focus in high-performance computing includes RDL interposer-layer technology and bridging technology (such as Connect-S). Multiple computation and networking customers have already entered qualification certification stages, with large-scale mass production expected in 2026. In addition, Amkor has significant advantages in high-density fan-out (HDFO), enabling thin, efficient interconnect solutions for next-gen smart phones and vehicle ADAS systems.

These routes are not completely competitive or mutually exclusive; they are targeted to serve different applications. High-end AI GPUs value bandwidth, yield, and maturity more; customized AI ASICs may value cost, supply flexibility, and multi-vendor strategy more; consumer electronics and edge AI products prioritize size, cost, and mass-production manufacturing capability.

It can be expected that the future advanced packaging market will not be dominated by TSMC alone, but will instead feature multiple technology routes and multiple suppliers coexisting.

How China’s advanced packaging can break the bottleneck

When advanced packaging is held by only a handful of companies, China’s semiconductor industry naturally can’t stay out. CoWoS capacity shortages and technical barriers reflect precisely the urgency for China to accelerate breakthroughs in advanced packaging.

The good news is that domestic players are catching up with full effort, and this advanced packaging race is not starting from zero.

OSAT giants such as JCET (长电科技), Tongfu Microelectronics (通富微电), and Huatian Technology (华天科技) have all already laid out 2.5D/3D packaging and Chiplet-related technology routes, with some products already entering mass production. For example, JCET announced in June 2026 that it will invest RMB 7.8 billion (1.38M yuan) to build a high-end advanced packaging plant in Shanghai Lingang, focusing on four areas: 2.5D/3D stacking, HBM3e, Chiplets, and CPO.

In addition, domestic companies such as Shenghe Jingwei (盛合晶微), Yongxi Electronics (甬矽电子), and Jingfang Technology (晶方科技) are also enhancing the value of the domestic supply chain through advanced packaging capabilities with their own specialties. The Third Phase of the Big Fund (大基金三期) has listed advanced packaging among its key support directions.

Compared with TSMC CoWoS, China’s makers may still have gaps in high-end AI GPU packaging—especially in HBM coordination, yield control, and customer ecosystem differences. But they have stronger local customer proximity for domestic AI chips and niche application scenarios.

More importantly, the widespread adoption of the Chiplet architecture provides a “change lanes and overtake” opportunity for domestic industry. When chips no longer chase a single ultra-best large die, but achieve high performance by stitching together multiple smaller chips, the share of value attributable to packaging will keep increasing—exactly the kind of area where China’s domestic OSAT industry has accumulated deep expertise.

Concluding remarks

The contest over CoWoS is far from over.

TSMC is expanding capacity; Intel, Samsung, and ASE are catching up; and domestic players are striving to break through. Whoever can laugh last in the advanced packaging competition will profoundly shape the AI chip landscape of the next decade. For China’s industry, this is both a challenge and a historic opportunity that cannot be missed.

Source of this article: Semiconductor Industry Observer

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