On-site institutional research: TSMC has won the current CPO race, while Samsung is betting on the next round

In the current “Co-Packaged Optics (CPO)” race among data centers, TSMC has seized the early lead with product progress from Broadcom and NVIDIA. Meanwhile, Samsung may be betting on the next phase.

On July 12, institutional research firm PhotonCap released an on-site investigation article, noting that CPO for switches has officially moved from technical validation to the customer deployment stage.

TSMC’s manufacturing and advanced packaging capabilities in this track have already been validated by the first batch of top-tier commercial projects. But the coming battlefield is far more complex than today’s switch CPO.

As optical I/O (optical interconnects) goes deeper into the inside of heterogeneous computing chip (XPU) and high-bandwidth memory (HBM) packages, whoever can take the lead in co-designing the synergy among these components will reshape the competitive dimensions of the entire industry.

On July 9, Samsung Electronics senior vice president Won-Kyoung Choi proposed at Nano Korea that the company is developing 2.xD advanced packaging, aiming to integrate HBM, logic chips, and silicon photonics chips into the same package. This direction is precisely targeting optical I/O for future AI computing packages.

Current TSMC leads in “switch CPO”

In today’s CPO market, TSMC is an undisputed leader.

Research shows that Broadcom’s 102.4Tbps CPO Ethernet switch based on TSMC’s COUPE (compact universal photonic engine) platform has already begun sending samples to early customers.

At the same time, NVIDIA’s Quantum-X photonic switch has started shipping, and Spectrum-X Ethernet photonic switches have entered production, with the first adopters including CoreWeave, Lambda, and Oracle.

The shared characteristic of this generation of products is: the optical engine is deployed close to the switch ASIC (application-specific integrated circuit). Its core manufacturing foundation is TSMC’s mature silicon photonics technology and its SoIC 3D stacking capability.

Under this architecture, the competition focus is on stacking and bonding of photonic integrated circuits (PIC) and electronic integrated circuits (EIC), as well as their integration with the switch package. At this stage, HBM is not a necessary component.

By contrast, Samsung’s publicly released “turnkey CPO solution” roadmap targets 2029. If shipment volume of today’s switch CPO and customer validation are used as the benchmark, Samsung has not yet formed a commercialization cadence synchronized with TSMC.

Power-consumption concerns drive optical engines “closer” to computing chips

The most core driver for moving optical I/O from traditional board-level toward inside-the-package is power consumption.

Samsung Foundry’s presentation materials prepared for OECC 2026 reveal a key step ladder:

• When pluggable optical modules are deployed at the board level, the energy per bit is about 10pJ;
• When the optical engine is placed on the substrate near the switch, energy drops to about 5pJ;
• If the optical I/O goes further into the vicinity of the XPU on the interposer, energy can be reduced significantly to about 2pJ.

The core logic behind this change is “shortening the transmission distance of electrical signals.” The closer the optical engine is to the computing chip, the shorter the electrical links become, and therefore less signal conditioning is needed to compensate for board-level routing and connector losses.

Therefore, advanced packaging is the key step for converting “physical power advantages” into “commercial product advantages.” This doesn’t mean CPO will immediately kill off pluggable optical modules; the two will coexist long term under different transmission-distance and power-budget constraints.

But Samsung’s data forecasts reveal the trend: the pluggable optical market’s CAGR is over 25%, while the CPO market’s CAGR is as high as 150% or more. Capital and R&D resources are flooding into highly integrated optical architectures.

Two CPO architectures: Samsung and TSMC’s misaligned competition

Mixing up “switch CPO” with “XPU-HBM optical I/O” severely underestimates the complexity of the competition in the next phase. In reality, these are two entirely different architectures:

The first is the current mainstream “switch CPO.” The optical engine sits beside the switch ASIC, which is exactly what Broadcom and NVIDIA’s products are. It addresses the interconnect power and signal integrity problems in high-bandwidth switching scenarios. TSMC’s moat lies in silicon photonics technology, advanced bonding, and switch-package integration.

The second is optical I/O packaging for an “XPU-HBM system.” Its structure configures XPU (or GPU), HBM, and an optical engine containing PIC and EIC together on the interposer. At this point, optical I/O is no longer a peripheral component of the switch; it truly becomes part of the “computing package.”

Samsung executives’ recently proposed 2.xD advanced packaging targets exactly this direction. The plan is to integrate HBM, logic chips, and silicon photonics chips into the same package, and to expand system packaging capability through panel-level redistribution layer (RDL) interposer, in order to meet the massive bandwidth throughput demands of AI data centers.

For investors, the competitive logic of these two architectures is completely different: the former tests single-process manufacturing and packaging; while the latter requires deep joint optimization of computing, memory, optics, and packaging from the “design-in” stage.

Samsung’s ace card and the real constraint of multi-die yield

Samsung’s biggest potential differentiator lies in its “trinity” business layout, as it simultaneously has HBM, logic chip foundry services, and a silicon photonics platform.

While TSMC has top-tier logic foundry, silicon photonics technology, and CoWoS packaging capability, it does not produce HBM itself.

Samsung, however, can connect HBM with its wafer foundry capabilities via SF4 base die-on-wafer, and build its own silicon photonics platform. This means Samsung can, in theory, complete joint co-design of HBM interfaces, logic I/O, optical engines, and thermal management internally, without having to look at the faces of external memory suppliers.

2.xD packaging faces extremely stringent testing challenges for multi-die yield. When logic chips, HBM, PIC, EIC, and the interposer are packed into a single package, failure of any one component will scrap the entire expensive package.

The increasing number of chips, expanding packaging area, and rising bonding complexity are multiplying yield pressure and cost risks.

Meanwhile, the opponent is not standing still. TSMC is advancing integration of COUPE with CoWoS packaging by accessing HBM through a mature external ecosystem.

On the other hand, memory giant SK hynix is also aggressively filling advanced packaging capabilities. Its advanced packaging factory in Indiana, USA, with an investment of $3.87 billion, will begin mass production in 2028, and it has already incorporated CPO into its technical R&D roadmap within memory systems.

Cross-domain collaboration among optics, memory, and packaging is becoming a common focus across the entire industrial chain.

Orders are the only standard to test who wins

TSMC won the first round of victory in switch CPO, with its advantage built on real customer sample deliveries, product shipments, and mass production progress.

Samsung, meanwhile, is betting on the next battle: attempting to achieve a “leapfrog” advantage in AI computing packaging by leveraging its vertical integration capabilities in HBM, logic, and silicon photonics.

But the market should not equate “technical roadmaps” with “commercial moats.”

Over the next 12 months, the only signal the industry is worth tracking is: whether the market will emerge with a named customer design order that explicitly requires HBM, logic chips, and optical I/O to be bound in the same package and have Samsung fabricate it.

If this order materializes, Samsung’s “trinity” will turn from paper assets into a real commercial weapon.

If it keeps being delayed without delivery, then TSMC’s flexible path built on leading process technology and the external HBM ecosystem will remain the safest choice for AI giants.

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