Gate News message, April 23 — TSMC unveiled new manufacturing and packaging technologies designed to make chips smaller and faster, while announcing it will continue using existing ASML EUV machines rather than adopting newer High-NA lithography tools.
The company’s A13 process is targeted to enter production in 2029, while N2U represents a lower-cost option for smartphone, laptop, and AI chips. By 2028, TSMC aims to package 10 large chips with 20 memory stacks, compared to Nvidia’s Vera Rubin design which features two compute chips and eight memory stacks.
The decision contrasts with competitors moving faster on High-NA technology. Intel has already installed ASML’s Twinscan EXE:5200B High-NA system and expects risk production in 2027 with volume output in 2028. Samsung received its first High-NA scanner in late 2025 and a second in the first half of 2026, while SK Hynix installed a High-NA EUV tool in September 2025. TSMC’s choice reflects cost and risk considerations rather than a full dismissal of High-NA EUV technology.
Analysts noted that challenges including heat management, material expansion, and cracking remain unresolved. ASML maintains a near-monopoly in EUV systems, with ZEISS SMT, Lam Research, and Applied Materials positioned to benefit from the spending wave. Chinese chipmaker SMIC remains unable to purchase EUV tools under export restrictions.
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