According to Korean media Etnews, Intel is evaluating the introduction of a "dual-sided hybrid architecture" for its 14A2 process — using a backside power delivery network as the primary power path while redistributing some front-side metal interconnect layers to handle auxiliary power signals and clock distribution. TSMC's N2 (2nm) has already completed stable mass production in 2025-2026, and Intel's time gap relative to its competitors is at least equivalent to one full process generation.
21nm Line Width Becomes a Physical Bottleneck: Metal Resistance Rises Exponentially, nTSV Architecture Cannot Withstand Required Current Density
According to Etnews, the 21nm M0 pitch target of Intel's 14A2 is becoming a physical bottleneck for existing architectures: when metal line width is reduced below 21nm, interconnect resistance rises exponentially; the nano-through-silicon via (nTSV) infrastructure originally designed for the BSPDN architecture can no longer alone withstand the current density required for normal transistor operation, leading to voltage drops that harm chip power efficiency and performance stability, and pose yield risks.
The dual-sided hybrid architecture is Intel's solution to overcome this physical bottleneck; the cost is a significant increase in interconnect design complexity, including coordinated planning of front- and back-side signal paths, timing closure, and yield control, which is far more difficult than a single-sided power delivery architecture.
Competitor Timelines: TSMC A14 Expected to Ship in 2028
According to the report, the process timelines and technology roadmaps of the three major foundries are as follows:
TSMC: N2 (2nm) has completed stable mass production in 2025-2026, aligning with the product launch rhythm of its largest customer Apple; A14 (1.4nm) is expected to ship to the market in 2028 — the same year Intel's 14A begins risk production.
Samsung Electronics: SF2Z is planned for commercialization in 2027; SF2Z stacks BSPDN on top of the GAA architecture already maturely verified at the 3nm node, with a single technological variable, theoretically allowing for faster yield curve convergence.
Intel: The 14A process is expected to enter risk production in 2028, with mass production in 2029; Intel's time gap relative to TSMC and Samsung is at least equivalent to one full process generation.
Citrini Analyst: Success Could Challenge TSMC's Dominance, Failure Risks Repeating Samsung's Decline
According to the report, Citrini analyst Jukan noted that Intel has been battling yield bottlenecks since introducing two innovative technologies — GAA transistors and BSPDN — in its 20A and 18A processes. Now, adding the dual-sided power architecture to 14A2 raises the technical risk stack far beyond Samsung's (Samsung's SF2Z has a simpler technological variable).
Jukan stated directly: "If Intel's strategic transformation succeeds, it could challenge TSMC's leading position; if it fails, it could trigger a catastrophic yield collapse and customer exodus, repeating the decline Samsung's foundry business suffered years ago."
The industry believes that the Fabless order locking situation within 18 months after the 14A PDK release will be the most important first indicator of the health of Intel's foundry business recovery.
FAQ
What are the main differences between Intel's 14A and 14A2 processes?
According to Etnews, 14A targets an M0 pitch of approximately 28nm and uses a pure BSPDN architecture (PowerDirect technology); 14A2 is a half-node optimization, aiming to compress the M0 pitch to about 21nm, increasing density by 1.3 times over the current 18A, and is evaluating the introduction of a dual-sided hybrid architecture to address the resistance and current density challenges brought by the 21nm line width.
When is Intel's 14A process expected to enter mass production?
According to Intel's current roadmap, the 14A process is expected to enter risk production in 2028 and reach mass production scale in 2029; the 14A PDK 0.9 version is expected to be released in October this year, and Intel plans to lock in major Fabless customer orders within the following 18 months.
Why is Intel evaluating a dual-sided hybrid architecture for 14A2?
According to Etnews, Intel's fundamental reason for evaluating the dual-sided hybrid architecture is: when metal line width is reduced below 21nm, interconnect resistance rises exponentially, and the existing nTSV architecture cannot alone withstand the required current density, causing voltage drops and harming chip power efficiency; the dual-sided hybrid architecture is a technological solution to overcome this physical bottleneck.
