Opening
Huawei formally announced the 'Tau (τ) Law' on May 25, 2026, at the International Circuits and Systems Symposium in Shanghai, marking China's first proposal of a guiding principle for global semiconductor industry development. He Tingbo, Huawei director and semiconductor business president, delivered the keynote speech titled 'Exploration and Practice of New Semiconductor Development Pathways.' The same day, He published a peer-reviewed paper titled 'A Time Scaling Theory for Multi-Layer Electronic Systems' on the Chinese Academy of Sciences' preprint platform, providing detailed technical explanation and theoretical foundation for the new law.
The Tau Law proposes replacing 'geometric scaling'—the traditional approach of shrinking transistor sizes—with 'time (τ) scaling' as the fundamental optimization principle for semiconductor and electronic system evolution. According to Huawei's framework, this shift responds to the reality that Moore's Law no longer delivers significant benefits after the 7-nanometer node, and advanced lithography technology access has become severely constrained and economically prohibitive for many chipmakers. By systematically compressing signal propagation delays through innovation techniques such as logic folding and continuously increasing transistor density, the Tau Law aims to achieve sustained semiconductor evolution without relying primarily on advancing process nodes.
The announcement triggered immediate market response: Chinese semiconductor stocks surged on May 25, with China Integrated Circuits (SMIC) trading near limit-up, Huahong Semiconductor approaching a 20% limit-up, and equipment suppliers Triotech (688072.SH) and Shengmei Shanghai (688082.SH) posting significant gains.
Time (τ) Scaling Replaces Geometric Scaling
The Tau Law fundamentally reframes the semiconductor industry's primary optimization target. Rather than focusing exclusively on shrinking transistor dimensions, it proposes systematic reduction of characteristic time constant τ—the time required for signals to propagate through each layer of the electronic system—from picosecond-level transistor switching to second-level data center workload response.
Historically, the semiconductor industry's primary task centered on one objective: reducing transistor size. Gordon Moore observed in 1965 that transistor density approximately doubled every two years. A decade later, Robert Dennard's scaling theory complemented this observation, demonstrating that proportional reduction of voltage and size could maintain constant electric field strength. Geometric scaling and Dennard scaling together enabled exponential improvements in performance-per-watt and performance-per-dollar over nearly fifty years.
According to He Tingbo's published paper, this industry contract has lost applicability. Beyond the 7-nanometer node, geometric scaling no longer delivers proportional benefits. Advanced chip design at the 2-nanometer node now exceeds $1 billion in development budget. For companies like Huawei lacking access to the most advanced lithography equipment, these constraints arrived earlier and carry more severe consequences.
Over the past six years, Huawei's semiconductor team conducted deep research across mobile SoCs, AI accelerators, system architecture, and packaging. Their conclusion: the answer lies not in adopting new process nodes or transistor architectures, but in fundamentally changing the optimization objective itself. Rather than geometric scaling, future electronic system development should pursue time scaling—systematically lowering the characteristic time constant τ across every layer of the stack, from picosecond-level transistor switching to second-level data center response times.
Based on this principle, Huawei has successfully designed and mass-produced 381 chips over the past six years. The company will release new Kirin smartphone chips this autumn that fully implement logic folding technology with substantially enhanced performance.
He Hui, Omdia's semiconductor analysis director for China, explained that the Tau Law's principle applies high-transmission, low-latency principles from communication networks to chip internals, rather than relying solely on advanced process nodes to create scaling space and increase transistor counts. He further noted that given advanced process constraints, Huawei combines its technical advantages with communication technology expertise and improved dielectric materials to overcome physical limits and pursue alternative technological breakthroughs.
Logic Folding as Core Technology
He Tingbo's paper identifies logic folding as the central technical implementation of the Tau Law. The paper argues that Moore's Law's essence is not geometric reduction but the technology delivering maximum impact to end users. Smaller transistors improve system performance because they switch faster. Denser interconnect lines improve performance because signal transmission distances shorten. Higher integration improves performance because data crosses fewer boundaries. Each technology generation fundamentally compresses time—from picoseconds to nanoseconds at device level, nanoseconds to microseconds at chip level, microseconds to seconds at system level. Spatial scaling serves merely as a tool for compressing time.
Therefore, time itself should function as the primary measurement standard. At every layer of the stack—transistor, circuit, chip, and system—a characteristic time constant τ can be defined and reducing it serves as the unified optimization objective. Geometric scaling becomes one technical approach among many, rather than the sole method.
Paul Triolo, partner and vice president at Albright Stonebridge Group and China technology policy lead, interpreted the Tau Law as follows: Huawei's approach is straightforward—future semiconductor progress no longer depends primarily on geometric size reduction but on compressing the effective time constant τ across device, circuit, chip, and system layers. At device level, this mechanism reduces resistance and capacitance. At circuit level, it means using three-dimensional 'logic folding' architecture to shorten wires and signal paths. At chip level, it means hardware-software architecture and silicon co-design. At system level, it means reducing interconnect latency through unified memory semantics and tightly integrated SuperPods.
Regarding logic folding specifically, Triolo explained that Huawei describes it as transitioning from traditional two-dimensional layout to vertical stacking architecture, where multiple logical layers fold upward along the Z-axis. Huawei's analogy: transitioning from single-story houses to multi-story buildings connected by elevators. The goal is direct: without complete dependence on transistor size reduction, reduce signal propagation distance, shorten critical paths, and increase effective transistor density to achieve performance improvements.
According to the paper, the first mass-production scale test of τ scaling occurred in mobile device applications. Smartphone SoCs possess unique characteristics: a single chip constitutes the entire system. Multi-socket parallel architectures cannot be implemented; even thousands of nodes cannot compensate for slow link speeds. All performance delivered to users originates from a single chip consuming only several watts and constrained by heat dissipation limits from handheld device form factors.
Furthermore, after 2020, as advanced process node access became restricted, the critical question became: with fixed process nodes, how can generational performance improvements continue on a single chip?
Huawei's answer: logic folding. Logic folding is a design methodology dividing digital, analog, and storage circuits into vertically stacked active layers following time scaling principles, achieving coordinated optimization between performance, power consumption, and area.
He Tingbo stated that the 'Kirin 2026' smartphone chip represents logic folding's first successful implementation. Based on entirely new free logic design principles, it extends from single-layer to dual-layer architecture and achieves substantial improvements in transistor density and related metrics. "We achieved a series of advances difficult to obtain through advanced process technology alone," He said. Such innovations will progressively reach production chips in 2027 and beyond.
"Over the next decade, we will continue moving toward comprehensive folding, even multi-layer folding, continuously optimizing full-stack performance from devices, circuits, chips, and systems," He stated.
Triolo noted this approach is not entirely technologically novel. The semiconductor industry has pursued this direction for years—NVIDIA's current advantage derives not only from transistor density but system-level integration; AMD pursues chiplet stacking and advanced packaging; Apple's M-series success owes substantially to memory localization and hardware-software vertical integration. "Huawei's approach distills these trends and elevates them into a comprehensive post-Moore's Law era solution," Triolo said.
According to the paper, logic folding on mobile SoCs achieved a 55% transistor density step-function increase and 41% energy efficiency gain at fixed device nodes (unchanged process technology). The paper projects that by 2031, transistor density will increase from 155 MT/mm² (million transistors per square millimeter) to 400+ MT/mm² at device and circuit levels. Huawei's official statement indicated that by 2031, advanced chips based on the Tau Law will achieve transistor density equivalent to 1.4-nanometer process technology.
Impact on China's Semiconductor Industry
In global semiconductor competition, China's semiconductor industry faces the greatest challenges and pressures due to advanced lithography technology constraints. However, Huawei's Tau Law and multiple chip prototypes provide a new direction for China's semiconductor industry—and the global semiconductor industry—to achieve continued evolution in the post-Moore's Law era.
From May 2020 to May 2026, Huawei designed and mass-produced 381 chips serving mobile, artificial intelligence, automotive, industrial, and infrastructure markets. Across this product portfolio, τ scaling theory received validation.
Huawei stated in its paper that looking forward, CPU core frequencies are projected to reach 4 GHz and above by 2029. Kirin SoC energy efficiency is projected to improve more than twofold within three to five years under typical usage scenarios. AI hardware integration is projected to increase more than 100-fold by 2035.
He Tingbo stated that from 2026 to 2035, as numerous exploratory technologies progressively become productized, transistor density will continue increasing, operating frequency will continue growing, and the company will continue releasing high-performance smartphone chips. "Our solution works and works well. Our new chips' performance can fully sustain continuous benchmarking against alternative pathways."
Regarding future semiconductor industry development, He Tingbo stated: "The future certainly belongs to open cooperation. Under the Tau Law pathway, we anticipate close collaboration with global scientists, engineers, and industry partners to jointly advance semiconductor and electronic industry development."
He Hui assessed that Huawei's disclosure itself demonstrates an attitude: pursuing system-level optimization rather than purely competing on physical limits represents a positive attempt as silicon-based Moore's Law approaches fundamental limits.
Hu Yanping, Shanghai University of Finance distinguished professor specializing in intelligent technology industries and intelligent economy research, characterized the Tau Law as essentially unlocking Huawei-style chip computing spatio-temporal perspectives: applying free logic transformation principles, physical optimization of time constants, logic folding for density increase, full-stack coordination for efficiency improvement, and system reconstruction for latency reduction. This represents a new framework distinct from previous perspectives emphasizing process precision, DUV multi-exposure, and yield rates, featuring multi-dimensional technology fusion evolution characteristics that involve not merely addition and optimization. Industry observers should examine not only logic folding but understand what the free logic design philosophy fundamentally represents.
Hu Yanping concluded that the Tau Law constitutes both theoretical innovation and practical exploration. "As the path progresses, it gradually extends far, moving beyond the familiar semiconductor industry landscape."
FAQ
Q: What is the Tau Law and how does it differ from Moore's Law?
A: The Tau Law, formally announced by Huawei on May 25, 2026, proposes replacing 'geometric scaling' (shrinking transistor sizes) with 'time (τ) scaling' (reducing signal propagation delays) as the guiding principle for semiconductor evolution. Moore's Law, based on transistor density doubling approximately every two years, no longer delivers proportional benefits beyond the 7-nanometer process node. The Tau Law addresses this by systematically reducing the characteristic time constant τ across all layers—from transistor switching (picoseconds) to data center response (seconds)—enabling performance improvements without relying primarily on advancing process nodes.
Q: What is logic folding and how does it work?
A: Logic folding is the core implementation technique of the Tau Law. It transitions from traditional two-dimensional chip layouts to three-dimensional vertical stacking, where multiple logical layers fold upward along the Z-axis. Using Huawei's analogy, it resembles transitioning from single-story houses to multi-story buildings connected by elevators. By reducing signal propagation distance, shortening critical paths, and increasing effective transistor density without relying on smaller process nodes, logic folding achieves performance improvements. On fixed process nodes, Huawei's implementation achieved 55% transistor density increase and 41% energy efficiency gain.
Q: What are Huawei's projected performance improvements from the Tau Law?
A: According to Huawei's published paper, CPU core frequencies are projected to reach 4 GHz and above by 2029. Kirin SoC energy efficiency is projected to improve more than twofold within three to five years under typical usage. AI hardware integration is projected to increase more than 100-fold by 2035. By 2031, advanced chips based on the Tau Law will achieve transistor density equivalent to 1.4-nanometer process technology.
