Google's TPU 8t Virgo network is impressive, with 47 Pb/s non-blocking bandwidth plus millions of chip extensions, pushing computational infrastructure to a new level.

Google discloses TPU 8t architecture, implementing rack interconnection through the Virgo network, using high-radix switches and a flat two-layer non-blocking topology, achieving a 4x bandwidth increase, connecting 134k chips with 47 Pb/s non-blocking bandwidth, and nearly linear scaling to 1.7K ExaFlops. TPU 8t adopts a 3D torus topology, with a single super pod of 9,600 chips, expandable via JAX/Pathways to over one million chips. Core technologies include SparseCore, VPU/MXU overlap and balancing, native FP4, and integrated Arm Axion CPUs, targeting evolution from dense large language models to large-scale mixture-of-experts and inference architectures.